On-chip silicon odometers for circuit aging characterization

John Keane, Xiaofei Wang, Pulkit Jain, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Abstract

The parametric shifts or circuit failures caused by Bias Temperature Instability (BTI) and other aging mechanisms in CMOS transistors have become more severe with shrinking device sizes and voltage margins. These mechanisms must be studied in order to develop accurate reliability models which are used to design robust circuits. Another option for addressing aging effects is to use on-chip reliability monitors that can trigger real-time adjustments to compensate for reduced performance or device failures. The need for efficient technology characterization and aging compensation is exacerbated by the rapid introduction of process changes, such as high-k/metal gate stacks and new transistor architectures.

Original languageEnglish (US)
Title of host publicationBias Temperature Instability for Devices and Circuits
PublisherSpringer New York
Pages679-717
Number of pages39
Volume9781461479093
ISBN (Electronic)9781461479093
ISBN (Print)1461479088, 9781461479086
DOIs
StatePublished - Jul 1 2014

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