The parametric shifts or circuit failures caused by Bias Temperature Instability (BTI) and other aging mechanisms in CMOS transistors have become more severe with shrinking device sizes and voltage margins. These mechanisms must be studied in order to develop accurate reliability models which are used to design robust circuits. Another option for addressing aging effects is to use on-chip reliability monitors that can trigger real-time adjustments to compensate for reduced performance or device failures. The need for efficient technology characterization and aging compensation is exacerbated by the rapid introduction of process changes, such as high-k/metal gate stacks and new transistor architectures.
|Original language||English (US)|
|Title of host publication||Bias Temperature Instability for Devices and Circuits|
|Publisher||Springer New York|
|Number of pages||39|
|ISBN (Print)||1461479088, 9781461479086|
|State||Published - Jul 1 2014|
Bibliographical notePublisher Copyright:
© Springer Science+Business Media New York 2014. All rights are reserved.