Observation of Higher Upset Rates in Multi-Bit Flip-Flops Utilized in Low Power Designs

Multi-bit flip-flops (MBFFs) are widely adopted in low-power digital designs due to their ability to reduce area and clock switching power by sharing clock buffers across multiple individual flip-flops. However, this clock resource sharing introduces new bit-upsets vulnerabilities in the form of single-event transients (SETs) within the shared clock buffer, distinct from standard storage-node single-event upset (SEU). This work presents neutron-induced soft error characterization results for MBFFs implemented with both standard and radiation-hardened dual interlocked storage cell (DICE) latches in a 0.9V, 28nm CMOS technology. Neutron irradiation experiment was conducted at the ChipIR facility in the Rutherford Appleton Laboratory, UK. A total of 84 test chips containing over 800,000 flip-flops were tested under multiple voltage conditions and data patterns. Upset mechanisms were classified into storage-node upsets, local clock buffer SETs, and global scan clock SETs. The results confirm that MBFFs, despite the use of DICE for hardened storage, exhibit significantly increased susceptibility to SETs in shared clock buffers. This study highlights an important trade-off between power efficiency and radiation resilience in multi-bit flip-flop designs, calling attention to the need for targeted mitigation strategies to ensure robust system operation in radiation prone environments.