OASYS: A framework for analog circuit synthesis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined.

Original languageEnglish (US)
Title of host publicationProc Second Annu IEEE ASIC Semin Exhib
Editors Anon
PublisherPubl by IEEE
StatePublished - Dec 1 1989
EventProceedings of the Second Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA
Duration: Sep 25 1989Sep 28 1989

Other

OtherProceedings of the Second Annual IEEE ASIC Seminar and Exhibit
CityRochester, NY, USA
Period9/25/899/28/89

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