Novel low-power shared division and square-root architecture using the GST algorithm

M. Kuhlmann, Keshab K Parhi

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Although SRT division and square-root approaches and GST division approach have been known for long time, square-root architectures based on the GST approach have not been proposed so far which do not require a final division/multiplication of the scale factor. A GST square-root architecture is developed without requiring either a multiplication to update the scaled square-root quotient in each iteration or a division/multiplication by the scaling factor after completing the square-root iterations. Additionally, quantitative comparison of speed and power consumption of GST and SRT division/square-root units are presented. Shared divider and square-root units are designed based on the SRT and the GST approaches, in minimally and maximally redundant radix-4 representations. Simulations demonstrate that the worst-case overall latency of the minimally-redundant GST architecture is 35% smaller compared to the SRT. Alternatively, for a fixed latency, the minimally-redundant GST architecture based division and square-root operations consume 32% and 28% less power, respectively, compared to the maximally-redundant SRT approach.

Original languageEnglish (US)
Pages (from-to)365-376
Number of pages12
JournalVLSI Design
Volume12
Issue number3
DOIs
StatePublished - Jan 1 2001
Externally publishedYes

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Keywords

  • Division
  • GST
  • Low-power architecture
  • SRT
  • Scaling
  • Square-root

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