Novel embedded low impedance design method approach for MMIC applications

E. Davies-Venn, Rhonda R Franklin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A simple method for creating low impedance lines using embedded structures is presented. Measured results in a edge embedded CPW architecture show a 50% reduction in length compared to a surface structure. The reduction is due to an increase in capacitance of the embedded design resulting from a larger capacitive area and effective dielectric constant. Index Terms -Silicon Embedded, Coplanar Waveguide and Low Impedance Lines.

Original languageEnglish (US)
Title of host publication2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Pages252-255
Number of pages4
DOIs
StatePublished - Dec 1 2006
Event2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - San Diego, CA, United States
Duration: Jan 18 2006Jan 20 2006

Publication series

Name2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Volume2006

Conference

Conference2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
CountryUnited States
CitySan Diego, CA
Period1/18/061/20/06

Fingerprint Dive into the research topics of 'Novel embedded low impedance design method approach for MMIC applications'. Together they form a unique fingerprint.

  • Cite this

    Davies-Venn, E., & Franklin, R. R. (2006). Novel embedded low impedance design method approach for MMIC applications. In 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers (pp. 252-255). [1587960] (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers; Vol. 2006). https://doi.org/10.1109/SMIC.2005.1587960