Abstract
This work presents a Steiner tree construction procedure, Maximum delay violation Elmore routing tree, to meet specified sink arrival time constraints. It is shown that the optimal tree requires the use of non-Hanan points. The procedure works in two phases: a minimum-delay Steiner Elmore routing tree is first constructed using a minor variant of the Steiner Elmore routing tree procedure, after which the tree is iteratively modified, using an efficient search method, to reduce its length. The search method exploits the piecewise concavity of the delay function to arrive at a solution efficiently. Experimental results show that this procedure works particularly well for technologies where the interconnect resistance dominates, and significant cost savings are shown to be generated.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 436-444 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 18 |
| Issue number | 4 |
| DOIs | |
| State | Published - 1999 |
| Event | Proceedings of the 1998 International Symposium on Physical Design, ISPD-98 - Monterey, CA, United States Duration: Apr 6 1998 → Apr 8 1998 |
Keywords
- Global-routing
- Interconnect
- Optimization
- Performance-optimization
- Physical-design
- Routing
- Very large scale integration (vlsi)