An fT = 8.5 GHz NPN BJT-based ASIC comparator, for use in analogto-digital converters (ADCs), was designed for optimum noise performance using process-derived device model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (Eni) and offset voltage (VOS) will be presented. Eni and VOS must be minimised for a high resolution comparator. An equivalent input noise voltage of less than 1.2 nV/√Hz was predicted and measured, which is approximately 1/3 that obtained from typical, commercially available, low-noise ADC comparators.
|Original language||English (US)|
|Title of host publication||1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 1992|
|Event||35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States|
Duration: Aug 9 1992 → Aug 12 1992
|Name||Midwest Symposium on Circuits and Systems|
|Conference||35th Midwest Symposium on Circuits and Systems, MWSCAS 1992|
|Period||8/9/92 → 8/12/92|
Bibliographical notePublisher Copyright:
© 1992 IEEE.