Noise performance optimization design for high-speed analog-to-digital converters

Robert W. Sandage, Stanley G. Burns

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An fT = 8.5 GHz NPN BJT-based ASIC comparator, for use in analogto-digital converters (ADCs), was designed for optimum noise performance using process-derived device model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (Eni) and offset voltage (VOS) will be presented. Eni and VOS must be minimised for a high resolution comparator. An equivalent input noise voltage of less than 1.2 nV/√Hz was predicted and measured, which is approximately 1/3 that obtained from typical, commercially available, low-noise ADC comparators.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages623-626
Number of pages4
ISBN (Electronic)0780305108
DOIs
StatePublished - Jan 1 1992
Externally publishedYes
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1992-August
ISSN (Print)1548-3746

Conference

Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
CountryUnited States
CityWashington
Period8/9/928/12/92

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  • Cite this

    Sandage, R. W., & Burns, S. G. (1992). Noise performance optimization design for high-speed analog-to-digital converters. In 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems (pp. 623-626). [271245] (Midwest Symposium on Circuits and Systems; Vol. 1992-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.1992.271245