Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces

Jian Xu, Anh Tuan Nguyen, Diu Khue Luu, Markus Drealan, Zhi Yang

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents the noise optimization of a novel switched-capacitor (SC) based neural interface architecture, and its circuit demonstration in a 0.13 μ m CMOS process. To reduce thermal noise folding ratio, and suppress kT/C noise, several noise optimization techniques are developed in the proposed architecture. First, one parasitic capacitance suppression scheme is developed to block noise charge transfer from parasitic capacitors to amplifier output. Second, one recording path-splitting scheme is proposed in the input sampling stage to selectively record local field potentials (LFPs), extracellular spikes, or both for reducing input noise floor, and total power consumption. Third, an auto-zero noise cancellation scheme is developed to suppress kT/C noise in the neural amplifier stage. A prototype neural interface chip was fabricated, and also verified in both bench-top, and In-Vivo experiments. Bench-top testings show the input-referred noise of the designed chip is 4.8 μ V from 1 Hz to 300 Hz, and 2.3 μ V from 300 Hz to 8 kHz respectively, and In-Vivo experiments show the peak-to-peak amplitude of the total noise floor including neural activity, electrode interface noise, and the designed chip is only around 20 μV. In comparison with conventional architectures through both circuit measurement and animal experiments, it is well demonstrated that the proposed noise optimization techniques can effectively reduce circuit noise floor, thus extending the application range of switched-capacitor circuits.

Original languageEnglish (US)
Article number9173719
Pages (from-to)1024-1035
Number of pages12
JournalIEEE transactions on biomedical circuits and systems
Volume14
Issue number5
DOIs
StatePublished - Oct 2020

Bibliographical note

Funding Information:
Manuscript received April 6, 2020; revised June 19, 2020 and July 27, 2020; accepted July 28, 2020. Date of publication August 21, 2020; date of current version October 15, 2020. This work was supported in part by the Hundred Talents Program at Zhejiang University, in part by the National Science Foundation under CAREER Award 1845709, and in part by the National Institutes of Health under Grant R21-NS111214-01. This paper was recommended by Associate Editor Prof. Jan Van der Spiegel. (Corresponding author: Jian Xu.) Jian Xu is with Frontiers Science Center for Brain, and Brain-Machine Integration, Zhejiang University, Hangzhou 3210058, China, and also with the Department of Biomedical Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: xujian84@zju.edu.cn).

Keywords

  • kT/C noise cancellation, noise optimization techniques
  • neural interface
  • parasitic capacitance suppression
  • path-splitting scheme
  • switched-capacitor circuits

PubMed: MeSH publication types

  • Journal Article

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