Abstract
The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 635-640 |
| Number of pages | 6 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 1989 |
| Event | IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA Duration: May 8 1989 → May 11 1989 |