Nibble-serial arithmetic processor designs via unfolding

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

Original languageEnglish (US)
Pages (from-to)635-640
Number of pages6
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Dec 1 1989

Fingerprint

Networks (circuits)
Numbering systems

Cite this

Nibble-serial arithmetic processor designs via unfolding. / Parhi, Keshab K.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 1, 01.12.1989, p. 635-640.

Research output: Contribution to journalArticle

@article{46bc0e07275040b69621789cc0d5a5ed,
title = "Nibble-serial arithmetic processor designs via unfolding",
abstract = "The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.",
author = "Parhi, {Keshab K}",
year = "1989",
month = "12",
day = "1",
language = "English (US)",
volume = "1",
pages = "635--640",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Nibble-serial arithmetic processor designs via unfolding

AU - Parhi, Keshab K

PY - 1989/12/1

Y1 - 1989/12/1

N2 - The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

AB - The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

UR - http://www.scopus.com/inward/record.url?scp=0024906909&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024906909&partnerID=8YFLogxK

M3 - Article

VL - 1

SP - 635

EP - 640

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -