### Abstract

The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W_{1}-b of a word or sample in a single cycle, and the complete word is input in W_{2} cycles, where W = W_{1}W_{2} is the word length. W_{1} need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

Original language | English (US) |
---|---|

Pages (from-to) | 635-640 |

Number of pages | 6 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 1 |

State | Published - Dec 1 1989 |

Event | IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA Duration: May 8 1989 → May 11 1989 |

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### Cite this

**Nibble-serial arithmetic processor designs via unfolding.** / Parhi, Keshab K.

Research output: Contribution to journal › Conference article

*Proceedings - IEEE International Symposium on Circuits and Systems*, vol. 1, pp. 635-640.

}

TY - JOUR

T1 - Nibble-serial arithmetic processor designs via unfolding

AU - Parhi, Keshab K.

PY - 1989/12/1

Y1 - 1989/12/1

N2 - The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

AB - The author proposes dedicated high-speed architectures for nibble-serial implementation of arithmetic operations (such as addition, multiplication, division, and square root) using a two's-complement fixed-point number system (all numbers assumed to lie between -1 and +1). Nibble-serial circuits are obtained by systematically applying the unfolding transformation on the corresponding bit-serial circuits. Nibble-serial arithmetic circuits input W1-b of a word or sample in a single cycle, and the complete word is input in W2 cycles, where W = W1W2 is the word length. W1 need not be 4 in a nibble-serial implementation, but can be any divisor of the word length.

UR - http://www.scopus.com/inward/record.url?scp=0024906909&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024906909&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024906909

VL - 1

SP - 635

EP - 640

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -