Abstract
A new circuit based on combining XOR gates and double pass-transistor logic has been developed for implementing a full adder. The main design objectives for these new circuits are low power consumption and full-voltage swing at a low supply voltage. The proposed full adder circuit is compared with previously known circuits and is shown to provide superior performance. The new and previous full adder circuits have been fully simulated using HSPICE with 0.4μm CMOS technology at a 2.0V supply voltage. An extensive analysis of a 8-bit carry-select adder establishes the superiority of the proposed circuit in that application.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 88-92 |
| Number of pages | 5 |
| Journal | Proceedings of the IEEE Great Lakes Symposium on VLSI |
| State | Published - Jan 1 1997 |
| Event | Proceedings of the 1997 7th Great Lakes Symposium on VLSI - Urbana-Champaign, IL, USA Duration: Mar 13 1997 → Mar 15 1997 |