New gate selection method for resizing to circuit performance optimization

Juho Kim, Yaun Chung Hsu, David H C Du

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

In the circuit model that outputs are latched and input vectors are successively applied by the same clock, the gate resizing approach to reduce the delay of the critical path may not improve its performance. In addition, the gate selection for resizing in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and vice versa. Our new gate selection methods prevent the delay of the longest sensitizable path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. Our algorithms are tested on ISCAS85 benchmark circuits and experimental results show that the clock period can be optimized efficiently with our gate selection methods.

Original languageEnglish (US)
Pages (from-to)461-464
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Jan 1 1996

Fingerprint

Dive into the research topics of 'New gate selection method for resizing to circuit performance optimization'. Together they form a unique fingerprint.

Cite this