Abstract
Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from Negative Bias Temperature Instability (NBTI) is of particular concern in deep submicron technology generations. While there has been significant effort at the device and circuit level to model and characterize the impact of NBTI, the analysis of NBTI's impact at the architectural level is still at its infancy. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed that evaluates timing degradation due to NBTI. The tool includes workload-based temperature and performance degradation analysis across a variety of technologies and operating conditions, revealing a complex interplay between factors influencing NBTI timing degradation.
Original language | English (US) |
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Pages (from-to) | 417-431 |
Number of pages | 15 |
Journal | International Journal of Parallel Programming |
Volume | 37 |
Issue number | 4 |
DOIs | |
State | Published - Aug 2009 |
Externally published | Yes |
Bibliographical note
Funding Information:Acknowledgements This project was supported by SRC’s GSRC Focus Center and NSF Grants 0702617, 0454123, 90207002, and 60870001. The authors would also like to thank Toyota for a generous donation towards this project.
Keywords
- Microprocessor reliability
- NBTI framework
- Negative bias temperature instability (NBTI)
- Reliable systems