Neutron-induced pulsewidth distribution of logic gates characterized using a pulse shrinking chain-based test structure

Keyphrases

• Neutron 100%
• Pulse Width 100%
• Logic Gates 100%
• Chain-based 100%
• Pulse Shrinking 100%
• Design Parameters 40%
• Single-event Transient 40%
• High-resolution 20%
• Transistor 20%
• Device Testing 20%
• Radiation Effects 20%
• Irradiation 20%
• Varying Length 20%
• Chain Length 20%
• Relative Impact 20%
• Threshold Voltage 20%
• Soft Error 20%
• Array-based 20%
• Planar CMOS 20%
• Operating Voltage 20%
• Distortion Effect 20%
• Neutron Radiation 20%
• Fin Field-effect Transistor (FinFET) 20%
• Transient Pulse 20%
• Logic Chain 20%
• Sampling Circuit 20%
• Near-threshold 20%
• High-density Array 20%

Engineering

• Test Structure 100%
• Logic Gate 100%
• Design Parameter 66%
• Measured Data 33%
• Operating Voltage 33%
• Irradiation Data 33%
• Sampling Circuit 33%
• High Resolution 33%
• Soft Error 33%
• Pulse Duration 33%