Neutron-induced pulsewidth distribution of logic gates characterized using a pulse shrinking chain-based test structure

Nakul Pande, Saurabh Kumar, Luke R Everson, Gyusung Park, Ibrahim Ahmed, Chris H. Kim

Research output: Contribution to journalArticlepeer-review


This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages (VTH), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD, VTH, device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types.

Original languageEnglish (US)
Pages (from-to)2736-2747
Number of pages12
JournalIEEE Transactions on Nuclear Science
Issue number12
StatePublished - Dec 1 2021

Bibliographical note

Publisher Copyright:
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  • Circuit reliability
  • Combinational logic
  • Neutron irradiation
  • Radiation effects
  • Single-bit upset (SBU)
  • Single-event effects
  • Single-event transient (SET)
  • Soft error rate


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