Graphene field effect transistors and capacitors that employ ultra-thin atomic layer deposited high-κ TiO2 dielectrics are demonstrated. Of the three TiO2 gate insulation schemes employed, the sequentially deposited HfO2:TiO2 gate insulator stack enabled the reduction of equivalent oxide thickness while simultaneously providing an ultra-thin gate insulation layer that minimized gate leakage current. The multilayer gate insulation scheme demonstrates a means for advanced device scaling in graphene-based devices.
Bibliographical noteFunding Information:
This work was supported by the Minnesota Partnership for Biotechnology and Medical Genomics. Parts of this work were carried out in the Characterization Facility (J. Myers), University of Minnesota, which receives partial support from NSF through the MRSEC program.