Multi-level reliability simulation for IC design

Ketul Sutaria; Jyothi Velamala; Yu Cao

doi:10.1109/ICSICT.2012.6467818

Multi-level reliability simulation for IC design

Ketul Sutaria, Jyothi Velamala, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.

Original language	English (US)
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6467818
State	Published - 2012
Externally published	Yes
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: Oct 29 2012 → Nov 1 2012

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	10/29/12 → 11/1/12

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10.1109/ICSICT.2012.6467818

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Sutaria, K., Velamala, J., & Cao, Y. (2012). Multi-level reliability simulation for IC design. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Article 6467818 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6467818

Multi-level reliability simulation for IC design. / Sutaria, Ketul; Velamala, Jyothi; Cao, Yu.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467818 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sutaria, K, Velamala, J & Cao, Y 2012, Multi-level reliability simulation for IC design. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6467818, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 10/29/12. https://doi.org/10.1109/ICSICT.2012.6467818

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AB - CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.

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Multi-level reliability simulation for IC design

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