Multi-Channel FFT Architectures Designed via Folding and Interleaving

Nanda K. Unnikrishnan; Keshab K. Parhi

doi:10.1109/ISCAS48785.2022.9937347

Multi-Channel FFT Architectures Designed via Folding and Interleaving

Nanda K. Unnikrishnan, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

Computing the FFT of a single channel is well understood in the literature. However, computing the FFT of multiple channels in a systematic manner has not been fully addressed. This paper presents a framework to design a family of multi-channel FFT architectures using folding and interleaving. Three distinct multi-channel FFT architectures are presented in this paper. These architectures differ in the input and output preprocessing steps and are based on different folding sets, i.e., different orders of execution.

Original language	English (US)
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	142-146
Number of pages	5
ISBN (Electronic)	9781665484855
DOIs	https://doi.org/10.1109/ISCAS48785.2022.9937347
State	Published - 2022
Event	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States Duration: May 27 2022 → Jun 1 2022

Publication series

Name	2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Conference

Conference	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/Territory	United States
City	Austin
Period	5/27/22 → 6/1/22

Bibliographical note

Funding Information:
This research was supported in part by the National Science Foundation under grant number CCF-1954749.

Publisher Copyright:
© 2022 IEEE.

Keywords

FFT
Folding
Interleaving
Multi-Channel FFT

Publisher link

10.1109/ISCAS48785.2022.9937347

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Unnikrishnan, N. K., & Parhi, K. K. (2022). Multi-Channel FFT Architectures Designed via Folding and Interleaving. In IEEE International Symposium on Circuits and Systems, ISCAS 2022 (pp. 142-146). (2022 IEEE International Symposium on Circuits and Systems (ISCAS)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS48785.2022.9937347

Multi-Channel FFT Architectures Designed via Folding and Interleaving. / Unnikrishnan, Nanda K.; Parhi, Keshab K.
IEEE International Symposium on Circuits and Systems, ISCAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 142-146 (2022 IEEE International Symposium on Circuits and Systems (ISCAS)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Unnikrishnan, NK & Parhi, KK 2022, Multi-Channel FFT Architectures Designed via Folding and Interleaving. in IEEE International Symposium on Circuits and Systems, ISCAS 2022. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers Inc., pp. 142-146, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, United States, 5/27/22. https://doi.org/10.1109/ISCAS48785.2022.9937347

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abstract = "Computing the FFT of a single channel is well understood in the literature. However, computing the FFT of multiple channels in a systematic manner has not been fully addressed. This paper presents a framework to design a family of multi-channel FFT architectures using folding and interleaving. Three distinct multi-channel FFT architectures are presented in this paper. These architectures differ in the input and output preprocessing steps and are based on different folding sets, i.e., different orders of execution.",

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note = "Funding Information: This research was supported in part by the National Science Foundation under grant number CCF-1954749. Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 ; Conference date: 27-05-2022 Through 01-06-2022",

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AB - Computing the FFT of a single channel is well understood in the literature. However, computing the FFT of multiple channels in a systematic manner has not been fully addressed. This paper presents a framework to design a family of multi-channel FFT architectures using folding and interleaving. Three distinct multi-channel FFT architectures are presented in this paper. These architectures differ in the input and output preprocessing steps and are based on different folding sets, i.e., different orders of execution.

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ER -

Multi-Channel FFT Architectures Designed via Folding and Interleaving

Abstract

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Keywords

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