Design-Technology Co-Optimization (DTCO) has become an important design methodology for making early decisions on technology, circuit, and system design parameters. This invited paper introduces various aspects of DTCO for MRAM development, ranging from SPICE compatible Magnetic Tunnel Junction (MTJ) device models, array level spin transfer torque magnetoresistive random access memory (STT-MRAM) power-performance-area (PPA) evaluation, scalability and variability studies of large-scale arrays, and novel read and write circuit techniques.
|Original language||English (US)|
|Title of host publication||2020 IEEE International Electron Devices Meeting, IEDM 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Dec 12 2020|
|Event||66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States|
Duration: Dec 12 2020 → Dec 18 2020
|Name||Technical Digest - International Electron Devices Meeting, IEDM|
|Conference||66th Annual IEEE International Electron Devices Meeting, IEDM 2020|
|City||Virtual, San Francisco|
|Period||12/12/20 → 12/18/20|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported in part by C-SPIN, one of the six SRC STARnet Centers, through MARCO and DARPA and in part by the NSF/SRC E2CDA Program.
© 2020 IEEE.