Dynamic binary translation (DBT) is widely used in system virtualization and many other important applications. To achieve a higher translation quality, a learning-based approach has been recently proposed to automatically learn semanticallyequivalent translation rules. Because translation rules directly impact the quality and performance of the translated host codes, one of the key issues is to collect as many translation rules as possible through minimal training data set. The collected translation rules should also cover (i.e. apply to) as many guest binary instructions or code sequences as possible at the runtime. For those guest binary instructions that are not covered by the learned rules, emulation has to be used, which will incur additional runtime overhead. Prior learning-based DBT systems only achieve an average of about 69% dynamic code coverage for SPEC CINT 2006. In this paper, we propose a novel parameterization approach to take advantage of the regularity and the well-structured format in most modern ISAs. It allows us to extend the learned translation rules to include instructions or instruction sequences of similar structures or characteristics that are not covered in the training set. More translation rules can thus be harvested from the same training set. Experimental results on QEMU 4.1 show that using such a parameterization approach we can expand the learned 2,724 rules to 86,423 applicable rules for SPEC CINT 2006. Its code coverage can also be expanded from about 69.7% to about 95.5% with a 24% performance improvement compared to enhanced learning-based approach.
|Original language||English (US)|
|Title of host publication||Proceedings - 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020|
|Publisher||IEEE Computer Society|
|Number of pages||12|
|State||Published - Oct 2020|
|Event||53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020 - Virtual, Athens, Greece|
Duration: Oct 17 2020 → Oct 21 2020
|Name||Proceedings of the Annual International Symposium on Microarchitecture, MICRO|
|Conference||53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020|
|Period||10/17/20 → 10/21/20|
Bibliographical noteFunding Information:
We are very grateful to our shepherd and the anonymous reviewers for their valuable feedback and comments. This work is supported in part by the National Natural Science Foundation of China (No. 61672160), Shanghai Municipal Science and TechnologyMajor Project (No. 2018SHZDZX01) and ZJLab, Shanghai Municipal Science and TechnologyMa-jor Project (No. 2017SHZDZX01), Shanghai Technology Development and Entrepreneurship Platform for Neuromorphic and AI SoC, the Shanghai Research and Innovation Functional Program (No. 17DZ2260900), and a faculty startup funding of the University of Georgia.
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