Abstract
Modular exponentiation and its constituent operation, modular multiplication, are fundamental to numerous public-key cryptography schemes including RSA. Efficient hardware implementations via ASIC or coprocessor approaches are essential to high-performance and low-power applications. New techniques are developed to aid in the design of both sequential and parallel implementations in the residue number system (RNS). A new sequential modular multiplication method suitable for smart cards is proposed which achieves the best known operation count for an all-modular-Arithmetic approach. Furthermore, a new technique is introduced to address the Montgomery (1985) scale factor in fully-parallel RNS implementations.
Original language | English (US) |
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Title of host publication | Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers |
Editors | Michael B. Matthews |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1312-1316 |
Number of pages | 5 |
ISBN (Electronic) | 0780357000, 9780780357006 |
DOIs | |
State | Published - 1999 |
Event | 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States Duration: Oct 24 1999 → Oct 27 1999 |
Publication series
Name | Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers |
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Volume | 2 |
Other
Other | 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 |
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Country/Territory | United States |
City | Pacific Grove |
Period | 10/24/99 → 10/27/99 |
Bibliographical note
Publisher Copyright:© 1999 IEEE.
Keywords
- Modular Exponentiation
- Modular Multiplacataon
- RSA
- Residue Number System