TY - JOUR
T1 - MOLAR
T2 - A cost-efficient, high-performance SSD-based hybrid storage cache
AU - Liu, Yi
AU - Ge, Xiongzi
AU - Huang, Xiaoxia
AU - Du, David H
PY - 2014/9/29
Y1 - 2014/9/29
N2 - This paper proposes a deMOtion-based, fLash-awARe hybrid storage cache model, named MOLAR, to effectively integrate Flash-based Solid-State Disks (SSDs) into traditional dynamic random access memory (DRAM)-based memory storage systems where SSDs serve as the Tier-2 cache, while DRAM is considered as the Tier-1 cache. We found that conventional cache algorithms designed for DRAM perform poorly in SSDs due to the limited write cycles and asymmetric read/write performance of Flash memory. In MOLAR, a Flash-aware I/O path structure is designed to adapt the asymmetric read and write performance of SSDs and, moreover, to reduce useless write operations. A new control metric, demotion count, is validated to wisely select the evicted blocks from DRAM to reside in the SSD. Besides, for SSD can improve internal data placement from data access hints, the Logical Block Addresses in the SSD are grouped into the long-lived region and the short-lived region self-adaptively via a heuristic control algorithm based on the change of the block demotion count. Through trace-driven simulations, the overall hit ratio in MOLAR outperforms two traditional policies by 1.44-5.34%. The average access latency in SSDs is reduced by 3.5× to 4.5×. Moreover, write amplification is effectively reduced by ∼36% in two typical Flash address-mapping policies.
AB - This paper proposes a deMOtion-based, fLash-awARe hybrid storage cache model, named MOLAR, to effectively integrate Flash-based Solid-State Disks (SSDs) into traditional dynamic random access memory (DRAM)-based memory storage systems where SSDs serve as the Tier-2 cache, while DRAM is considered as the Tier-1 cache. We found that conventional cache algorithms designed for DRAM perform poorly in SSDs due to the limited write cycles and asymmetric read/write performance of Flash memory. In MOLAR, a Flash-aware I/O path structure is designed to adapt the asymmetric read and write performance of SSDs and, moreover, to reduce useless write operations. A new control metric, demotion count, is validated to wisely select the evicted blocks from DRAM to reside in the SSD. Besides, for SSD can improve internal data placement from data access hints, the Logical Block Addresses in the SSD are grouped into the long-lived region and the short-lived region self-adaptively via a heuristic control algorithm based on the change of the block demotion count. Through trace-driven simulations, the overall hit ratio in MOLAR outperforms two traditional policies by 1.44-5.34%. The average access latency in SSDs is reduced by 3.5× to 4.5×. Moreover, write amplification is effectively reduced by ∼36% in two typical Flash address-mapping policies.
KW - access hints
KW - demotion count
KW - hybrid storage cache
KW - solid-state drives
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U2 - 10.1093/comjnl/bxu156
DO - 10.1093/comjnl/bxu156
M3 - Article
AN - SCOPUS:84940665370
SN - 0010-4620
VL - 58
SP - 2061
EP - 2078
JO - Computer Journal
JF - Computer Journal
IS - 9
ER -