Module selection and data format conversion for cost-optimal DSP synthesis

Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations


In high level synthesis each node of a synchronous data-flow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule.

Original languageEnglish (US)
Pages (from-to)322-329
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
StatePublished - Dec 1 1994
EventProceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 6 1994Nov 10 1994


Dive into the research topics of 'Module selection and data format conversion for cost-optimal DSP synthesis'. Together they form a unique fingerprint.

Cite this