The average power consumption is proportional to the average value of transition activity, i.e., transition probability, and the variance of transition activity determines the strength of power grid noise. In this paper, for the first time, a simple accurate model for estimating the variance of transition activity was proposed, and the dual bit type (DBT) model for estimating the average transition activity was further developed. The model for estimating transition activity variance is based on linearly modeling the spatial correlation of bit-level transition activity, which leads to low computational complexity for computing the variance with very good estimation accuracy. The previous DBT model is made complete with the equation derived in this paper for computing the transition probability beyond the break-point BP1. In addition to DSP computational architecture and algorithm designs, the proposed simple models are of great significance for power grid noise decoupling and chip floor-planning designs.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings of the IEEE Great Lakes Symposium on VLSI|
|State||Published - 2001|
|Event||11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States|
Duration: Mar 22 2001 → Mar 23 2001