Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

Keyphrases

• On-chip Interconnects 100%
• Electrical Effect 100%
• Process-based 50%
• Process Improvement 50%
• Experimental Data Analysis 50%
• Physical Analysis 50%
• Performance Considerations 50%
• Damascene Process 50%

Engineering

• Interconnects 100%
• Electrical Effect 100%
• Process Improvement 50%
• Design Stage 50%
• Metrics 50%
• Process Stage 50%
• Damascene Process 50%