Modeling subthreshold leakage current in general transistor networks

Paulo F. Butzen, André I. Reis, Chris H. Kim, Renato P. Ribas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging VLSI Technologies and Architectures
Pages512-513
Number of pages2
DOIs
StatePublished - Nov 28 2007
EventIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil
Duration: Mar 9 2007Mar 11 2007

Other

OtherIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/TerritoryBrazil
CityPorto Alegre
Period3/9/073/11/07

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