Modeling subthreshold leakage current in general transistor networks

Paulo F. Butzen; André I. Reis; Chris H. Kim; Renato P. Ribas

doi:10.1109/ISVLSI.2007.68

Modeling subthreshold leakage current in general transistor networks

Paulo F. Butzen, André I. Reis, Chris H. Kim, Renato P. Ribas

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging VLSI Technologies and Architectures
Pages	512-513
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2007.68
State	Published - Nov 28 2007
Event	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: Mar 9 2007 → Mar 11 2007

Other

Other	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/Territory	Brazil
City	Porto Alegre
Period	3/9/07 → 3/11/07

Publisher link

10.1109/ISVLSI.2007.68

Find It

Find It at U of M Libraries

Cite this

Butzen, PF, Reis, AI, Kim, CH & Ribas, RP 2007, Modeling subthreshold leakage current in general transistor networks. in Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208976, pp. 512-513, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brazil, 3/9/07. https://doi.org/10.1109/ISVLSI.2007.68

@inproceedings{5928b363213e43419974d07191351465,

title = "Modeling subthreshold leakage current in general transistor networks",

abstract = "An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.",

author = "Butzen, {Paulo F.} and Reis, {Andr{\'e} I.} and Kim, {Chris H.} and Ribas, {Renato P.}",

year = "2007",

month = nov,

day = "28",

doi = "10.1109/ISVLSI.2007.68",

language = "English (US)",

isbn = "0769528961",

pages = "512--513",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 ; Conference date: 09-03-2007 Through 11-03-2007",

}

TY - GEN

T1 - Modeling subthreshold leakage current in general transistor networks

AU - Butzen, Paulo F.

AU - Reis, André I.

AU - Kim, Chris H.

AU - Ribas, Renato P.

PY - 2007/11/28

Y1 - 2007/11/28

N2 - An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.

AB - An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.

UR - http://www.scopus.com/inward/record.url?scp=36348958942&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=36348958942&partnerID=8YFLogxK

U2 - 10.1109/ISVLSI.2007.68

DO - 10.1109/ISVLSI.2007.68

M3 - Conference contribution

AN - SCOPUS:36348958942

SN - 0769528961

SN - 9780769528960

SP - 512

EP - 513

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI

T2 - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07

Y2 - 9 March 2007 through 11 March 2007

ER -

Modeling subthreshold leakage current in general transistor networks

Abstract

Other

Publisher link

Find It

Other files and links

Fingerprint

Cite this