@inproceedings{a903099df14c439c8073160c9ac0e7ff,
title = "Modeling of dynamic threshold voltage of high K gate stack and application in FinFET reliability simulation",
abstract = "A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (IJ) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of I d is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.",
author = "Yun Ye and Hongyu He and Chenyue Ma and Cheng Wang and Aixi Zhang and Jin He and Yu Cao",
year = "2012",
language = "English (US)",
isbn = "9781466562752",
series = "Technical Proceedings of the 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012",
pages = "428--431",
booktitle = "Nanotechnology 2012",
note = "Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2012 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2012 ; Conference date: 18-06-2012 Through 21-06-2012",
}