Abstract
This paper is focused on modeling of capacitor voltage imbalance in N-level flying capacitor multilevel (FCML) converters in the presence of imperfections in timing of control signals. A general state-space representation is developed to facilitate applications of two time-domain modeling methods: An exact numerical steady-state solution based on the augmented state-space approach, and a simpler approach based on linear-ripple inductor-current approximation. Examples of 4-level and 5-level FCML converters are examined to show how voltage imbalance depends on control signal timing mismatches, circuit parameter values, and N. It is shown how substantial differences between even-level and odd-level FCML converters can be related to rank reduction in the linear-ripple model under ideal timing conditions. Modeling results are verified by circuit simulations and experiments on a reconfigurable FCML prototype.
| Original language | English (US) |
|---|---|
| Title of host publication | 2019 IEEE 20th Workshop on Control and Modeling for Power Electronics, COMPEL 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728118420 |
| DOIs | |
| State | Published - Jun 2019 |
| Externally published | Yes |
| Event | 20th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2019 - Toronto, Canada Duration: Jun 17 2019 → Jun 20 2019 |
Publication series
| Name | 2019 IEEE 20th Workshop on Control and Modeling for Power Electronics, COMPEL 2019 |
|---|
Conference
| Conference | 20th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2019 |
|---|---|
| Country/Territory | Canada |
| City | Toronto |
| Period | 6/17/19 → 6/20/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
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