Modeling and verification of high-speed wired links with Verilog-AMS

Keyphrases

• Verilog-AMS 100%
• System Level 50%
• Behavioral Modeling 50%
• Design Verification 50%
• Input Signals 50%
• Mixed-signal Design 50%
• Circuit Model 50%
• Built-in-self-test (BiST) 50%
• Link Design 50%
• Overall Design 50%
• Behavioral Description 50%
• Path Search 50%
• Description Language 50%
• Jitter Tolerance 50%
• Mixed-mode Simulation 50%
• Design Search 50%
• Language Mode 50%
• Test Verification 50%

Engineering

• Simulation Result 100%
• Input Signal 100%
• Mixed Mode 100%
• Built-in Self Test 100%
• Design Verification 100%
• Critical Path 100%
• Behavioral Modeling 100%
• Jitter Tolerance 100%

Computer Science

• Verilog 100%
• Critical Path 50%
• Behavioral Description 50%
• Mixed-Mode Simulation 50%
• build-in self-test 50%
• Design Verification 50%