Modeling and verification of high-speed wired links with Verilog-AMS

Ming Ta Hsieh, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of Verilog-AMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included.

Original languageEnglish (US)
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages2105-2108
Number of pages4
StatePublished - Dec 1 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: May 21 2006May 24 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period5/21/065/24/06

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