Modeling and verification of high-speed wired links with Verilog-AMS

Ming Ta Hsieh; Gerald E. Sobelman

Modeling and verification of high-speed wired links with Verilog-AMS

Ming Ta Hsieh, Gerald E. Sobelman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of Verilog-AMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included.

Original language	English (US)
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	2105-2108
Number of pages	4
State	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: May 21 2006 → May 24 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	5/21/06 → 5/24/06

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Modeling and verification of high-speed wired links with Verilog-AMS. / Hsieh, Ming Ta; Sobelman, Gerald E.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 2105-2108 1693032 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hsieh, MT & Sobelman, GE 2006, Modeling and verification of high-speed wired links with Verilog-AMS. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693032, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2105-2108, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 5/21/06.

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AB - Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of Verilog-AMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included.

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Modeling and verification of high-speed wired links with Verilog-AMS

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