This paper demonstrates how equivalent-circuit representations of grid-following power-electronic inverters can be realized within a SPICE-based development environment using common circuit components and VerilogA code. This facilitates computationally lean simulations of inverter networks leveraging the strengths of SPICE in large-scale simulations. We validate the approach with time-domain simulations for a modified version of the IEEE standard 118-bus system modeled in Virtuoso (a SPICE-based solver). Simulation results are compared-focusing on accuracy and computation speed-with results from a commonly used power-electronics simulation package. We note a significant decrease in simulation time with comparable signal resolution when simulating the network in SPICE.
|Original language||English (US)|
|Title of host publication||2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - May 1 2021|
|Event||53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of|
Duration: May 22 2021 → May 28 2021
|Name||2021 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Conference||53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021|
|Country/Territory||Korea, Republic of|
|Period||5/22/21 → 5/28/21|
Bibliographical noteFunding Information:
This work was supported in part by the UMN Undergraduate Research Opportunities Program, National Science Foundation grant 1453921, U.S. Department of Energy’s Office of Energy Efficiency and Renewable Energy (EERE) under Solar Energy Technologies Office (SETO) Agreement Number EE0009025, and the Washington Research Foundation.
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