@inproceedings{f5758ff9bf8a4419bc434a1dd2466845,
title = "Modeling and estimating leakage current in series-parallel CMOS networks",
abstract = "This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.",
keywords = "CMOS gates, Leakage current modeling, Static power dissipation",
author = "Butzen, {Paulo F.} and Reis, {Andre I.} and Kim, {Chris H.} and Ribas, {Renato P.}",
year = "2007",
doi = "10.1145/1228784.1228852",
language = "English (US)",
isbn = "159593605X",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
pages = "269--274",
booktitle = "GLSVLSI'07",
note = "17th Great Lakes Symposium on VLSI, GLSVLSI'07 ; Conference date: 11-03-2007 Through 13-03-2007",
}