Modeling and estimating leakage current in series-parallel CMOS networks

Paulo F. Butzen, Andre I. Reis, Chris H. Kim, Renato P. Ribas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.

Original languageEnglish (US)
Title of host publicationGLSVLSI'07
Subtitle of host publicationProceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages269-274
Number of pages6
DOIs
StatePublished - Oct 1 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
Duration: Mar 11 2007Mar 13 2007

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CountryItaly
CityStresa-Lago Maggiore
Period3/11/073/13/07

Keywords

  • CMOS gates
  • Leakage current modeling
  • Static power dissipation

Fingerprint Dive into the research topics of 'Modeling and estimating leakage current in series-parallel CMOS networks'. Together they form a unique fingerprint.

Cite this