Model for the coanalysis of hardware and software architectures

Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

Successful multiprocessor system design for complex real-time embedded applications requires powerful and comprehensive, yet cost-effective, productive, and maintainable modeling. The multi-disciplinary, VHDL-based modeling library developed by the Honeywell Technology Center places heavy emphasis on multiprocessing and distributed communications. These models focus on detailed hardware performance analysis along with multiple abstraction levels for software representation and evaluation. This paper will detail the processor model which provides the key element for the coanalysis of hardware and software system architectures.

Original languageEnglish (US)
Pages94-103
Number of pages10
StatePublished - Jan 1 1996
EventProceedings of the 1996 4th International Workshop on Hardware/Software Co-Design (Codes/CASHE'96) - Pittsburgh, PA, USA
Duration: Mar 18 1996Mar 20 1996

Other

OtherProceedings of the 1996 4th International Workshop on Hardware/Software Co-Design (Codes/CASHE'96)
CityPittsburgh, PA, USA
Period3/18/963/20/96

Fingerprint Dive into the research topics of 'Model for the coanalysis of hardware and software architectures'. Together they form a unique fingerprint.

  • Cite this

    Rose, F., Carpenter, T., Kumar, S., Shackleton, J., & Steeves, T. (1996). Model for the coanalysis of hardware and software architectures. 94-103. Paper presented at Proceedings of the 1996 4th International Workshop on Hardware/Software Co-Design (Codes/CASHE'96), Pittsburgh, PA, USA, .