MMV: Metamodeling based microprocessor validation environment

Ajit Dingankar, Deepak A. Mathaikutty, Sreekumar V. Kodakara, Sandeep Shukla, David Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges, The systematic- validation approach starts with defining the correct beliaviors of the hardware and software components and their interactions. This requires a new modeling paradigm that supports multiple levels or abstraction. Mutual consistency of models at adjacent levels is crucial for manual refinement of models from the full chip level to production RTL, which is likely to remain the dominant design methodology of complex microprocessors in the near future." In this work, we present MMV, a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage and test generation tools. We illustrate the functionalities in MMV by modeling a 32 bit RISC processor at the system, instruction set architecture and microarchitecture levels. "We show by examples how consistency across levels is enforced during modefing and also how to generate constraints for automatic test generation.

Original languageEnglish (US)
Title of host publicationProceedings - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
Pages143-148
Number of pages6
DOIs
StatePublished - 2006
Event11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06 - Monterey, CA, United States
Duration: Nov 8 2006Nov 10 2006

Publication series

NameProceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
ISSN (Print)1552-6674

Other

Other11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
CountryUnited States
CityMonterey, CA
Period11/8/0611/10/06

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