TY - JOUR
T1 - MMM
T2 - Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs
AU - Lin, Yishuang
AU - Li, Yaguang
AU - Madhusudan, Meghna
AU - Sapatnekar, Sachin S.
AU - Harjani, Ramesh
AU - Hu, Jiang
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2024
Y1 - 2024
N2 - Performance modeling is a key bottleneck for analog design automation. Although machine learning-based models have advanced the state-of-the-art, they have so far suffered from huge data preparation cost, very limited reusability, and inadequate accuracy for large circuits. We introduce ML-based macro-modeling techniques to mitigate these problems for linear analog ICs and ADC/DACs. The modeling techniques are based on macro-models, which can be assembled to evaluate circuit system performance, and more appealingly can be reused across different circuit topologies. On representative testcases, our method achieves more than 1700× speedup for data preparation and remarkably smaller model errors compared to recent ML approaches. It also attains 3600× acceleration over SPICE simulation with very small errors and reduces data preparation time for an ADC design from 40 days to 9.6 h.
AB - Performance modeling is a key bottleneck for analog design automation. Although machine learning-based models have advanced the state-of-the-art, they have so far suffered from huge data preparation cost, very limited reusability, and inadequate accuracy for large circuits. We introduce ML-based macro-modeling techniques to mitigate these problems for linear analog ICs and ADC/DACs. The modeling techniques are based on macro-models, which can be assembled to evaluate circuit system performance, and more appealingly can be reused across different circuit topologies. On representative testcases, our method achieves more than 1700× speedup for data preparation and remarkably smaller model errors compared to recent ML approaches. It also attains 3600× acceleration over SPICE simulation with very small errors and reduces data preparation time for an ADC design from 40 days to 9.6 h.
KW - Electronic design automation
KW - machine learning
KW - macro modeling
KW - performance modeling
UR - http://www.scopus.com/inward/record.url?scp=85196486164&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85196486164&partnerID=8YFLogxK
U2 - 10.1109/tcad.2024.3416894
DO - 10.1109/tcad.2024.3416894
M3 - Article
AN - SCOPUS:85196486164
SN - 0278-0070
VL - 43
SP - 4740
EP - 4752
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 12
ER -