Abstract
Traditional logic optimization relies on proxy metrics to approximate post-mapping performance and area, which may not correlate well with post-mapping delay and area. This paper explore a ground-truth-based optimization flow that directly incorporates the post-mapping delay and area during optimization using decision tree-based machine learning models.
| Original language | English (US) |
|---|---|
| Title of host publication | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9783982674100 |
| DOIs | |
| State | Published - 2025 |
| Event | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, France Duration: Mar 31 2025 → Apr 2 2025 |
Publication series
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
|---|---|
| ISSN (Print) | 1530-1591 |
Conference
| Conference | 2025 Design, Automation and Test in Europe Conference, DATE 2025 |
|---|---|
| Country/Territory | France |
| City | Lyon |
| Period | 3/31/25 → 4/2/25 |
Bibliographical note
Publisher Copyright:© 2025 EDAA.
Keywords
- Logic synthesis
- PPA
- machine learning