Abstract
The layout area and power consumption of a binary-weighted capacitive digital-to-analog converter (DAC) increases exponentially with the number of bits. To meet linearity targets, unit capacitors should be large enough to limit errors caused by various sources of noise and those due to mismatch. This work proposes a systematic approach for minimizing the unit capacitance value that optimizes the linearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, as well as the impact of flicker and thermal noise.
| Original language | English (US) |
|---|---|
| Title of host publication | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9783981926378 |
| DOIs | |
| State | Published - 2023 |
| Event | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Antwerp, Belgium Duration: Apr 17 2023 → Apr 19 2023 |
Publication series
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
|---|---|
| Volume | 2023-April |
| ISSN (Print) | 1530-1591 |
Conference
| Conference | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 |
|---|---|
| Country/Territory | Belgium |
| City | Antwerp |
| Period | 4/17/23 → 4/19/23 |
Bibliographical note
Funding Information:This work is supported in part by the Semiconductor Research Corporation (SRC) and by the DARPA IDEA program (as part of the ALIGN project under SPAWAR Contract N660011824048).
Publisher Copyright:
© 2023 EDAA.