MIMO transceiver design based on a modified geometric mean decomposition

Wen Chih Kan, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

We present a MIMO joint transceiver design that can run at 350 MHz on a Xilinx Virtex-4 xc4vlx200ffl513-12 FPGA, The implementation is an 8 × 8 MIMO transceiver with a 16-QAM symbol constellation. This system can provide data throughput of 11.2 Gbps. The design is based on a modified Geometric Mean Decomposition (GMD) for a flat fading MIMO channel using VBLAST MIMO detection. The design flow uses Matlab Simulink as the model builder followed by the Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages677-680
Number of pages4
StatePublished - 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: May 27 2007May 30 2007

Other

Other2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
CountryUnited States
CityNew Orleans, LA
Period5/27/075/30/07

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