Abstract
We present a MIMO joint transceiver design that can run at 350 MHz on a Xilinx Virtex-4 xc4vlx200ffl513-12 FPGA, The implementation is an 8 × 8 MIMO transceiver with a 16-QAM symbol constellation. This system can provide data throughput of 11.2 Gbps. The design is based on a modified Geometric Mean Decomposition (GMD) for a flat fading MIMO channel using VBLAST MIMO detection. The design flow uses Matlab Simulink as the model builder followed by the Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Pages | 677-680 |
Number of pages | 4 |
State | Published - 2007 |
Event | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: May 27 2007 → May 30 2007 |
Other
Other | 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 |
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Country/Territory | United States |
City | New Orleans, LA |
Period | 5/27/07 → 5/30/07 |