A design including exchange coupled composite (ECC) bits in hexagonal arrays and a multi-pole write head is proposed to meet the requirement of 9.7 × 10 -4 bit error rate, 4 nm magnetic fly height, 5 switching field distribution, 5 synchronization error, and 5 jitter error to achieve 2.9 Tbits/in. 2 bit-patterned recording. Our head design writes two staggered tracks in a single pass and has maximum perpendicular field gradients of 580 Oe/nm along the down-track direction and 476 Oe/nm along the cross-track direction.
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The author would like to thank Manfred Schabes for valuable discussion. This work was supported by IDEMA/ASTC.