Microarchitecture-aware floorplanning using a statistical design of experiments approach

Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar

Research output: Contribution to journalConference articlepeer-review

30 Scopus citations


Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi-cycle delays. Although such a wire pipelining strategy allows higher operating frequencies, it can reduce the delivered performance of a microarchitecture, since the extra flip-flops inserted may increase the operation latencies and stall cycles. Moreover, the addition of latencies on some wires can have a large impact on the overall performance while other wires are relatively insensitive to additional latencies. This varying sensitivity suggests the need for a throughput-aware strategy for pipelining the interconnects that interacts closely with the physical design step, which determines the lengths of these multicycle wires. We use a statistical design of experiments strategy based on a multifactorial design, which intelligently uses a limited number of simulations to rank the importance of the wires. When applied at the floorplanning level, our results show improvements both in the overall system performance and in the total wire length when compared with an existing technique.

Original languageEnglish (US)
Article number35.1
Pages (from-to)579-584
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005


  • Floorplanning
  • Microarchitecture
  • Wire pipelining


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