Method for systematic power consumption modeling and optimization of pipeline ADC

On the demands of low power applications, the systematic power consumption of pipeline Analog-to-Digital converters (ADC) was researched and analyzed. Some power related factors including the current of the residue amplifiers, the scaling down of the stage accuracy, the thermal noise limitation, the optimization scaling down factor of capacitances as well as the front-end sampling hold circuits were discussed in details. Based on it, the system power consumption modeling was put forwards and the total dominant power consumption was derived. A hybrid _search algorithm was employed to optimize the capacitance and resolution of each stage simultaneously. And a CAD tool was developed to implement the whole optimization process. By using it, the system structure of a 10~15 bits pipeline ADCs was optimized. And the results of a 14-bit 100MS · s ^-1 pipeline ADC were shown in detail.