Metal gate work function engineering on gate leakage of MOSFETs

Yong Tian Hou, Ming Fu Li, Tony Low, Dim Lee Kwong

Research output: Contribution to journalArticlepeer-review

60 Scopus citations

Abstract

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO2 and HfO2 gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function Φ B of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of ΦB reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap ΦB results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-κ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.

Original languageEnglish (US)
Pages (from-to)1783-1789
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume51
Issue number11
DOIs
StatePublished - Nov 2004

Bibliographical note

Funding Information:
Manuscript received January 19, 2004; revised May 12, 2004. This work was supported by the Singapore A STAR under Grant R263-000-267-305. The review of this paper was arranged by Editor M.-C. Chang. Y.-T. Hou and M.-F. Li are with the Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260, and also with the Institute of Microelectronics, Singapore 177685. T. Low is with the Silicon Nano Device Lab, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260. D.-L. Kwong is with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX 78712 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TED.2004.836544

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