Memory size reduction for LDPC layered decoders

Shuang Zhao, Xiaofang Zhou, Fanglong Ying, Gerald E Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

LDPC coding has attracted much attention due to its high performance, and it has been widely used in telecommunication systems. This paper focuses on the decoder hardware architecture, especially on memory size reduction, which is an important part of the entire area cost. The design has been post-layout simulated using a UMC 0.18 micron technology at a clock speed of 74 MHz. Using the proposed 3-level memory structure together with the described control logic, the required number of bits of memory can be reduced by up to 34.9% compared to prior approaches.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages426-429
Number of pages4
DOIs
StatePublished - Dec 1 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: Dec 6 2010Dec 9 2010

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period12/6/1012/9/10

Keywords

  • LDPC
  • decoder
  • hierarchical memory organization
  • layered decoding
  • low density parity check code

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