Materials and processes for high k gate stacks: Results from the FEP transition center

C. M. Osburn, S. A. Campbell, A. Demkov, E. Eisenbraun, E. Garfunkel, T. Gustafsson, A. I. Kingon, J. Lee, D. J. Lichtenwalner, G. Lucovsky, T. P. Ma, J. P. Maria, V. Misra, R. J. Nemanich, G. N. Parsons, D. G. Schlom, S. Stemmer, R. M. Wallace, J. Whitten

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

A wide variety of materials and processes for high k dielectrics and metal gate electrodes have been studied as replacements for poly-Si/SiO2 or SiON in advanced CMOS devices. Care must be taken with the interfacial layer to control not only the nitrogen content but its spatial location. Nanocrystallization of the high k dielectric and the corresponding formation of charge and trapping levels associated with defects in the dielectric present one of the current challenges. Control of the workfunction of the gate electrode is shown to depend on many variables, including oxygen content and the material used for the capping layer on the metal gate. The hafnium oxide family of materials, along with metal alloy gates, is seen to provide the best solution for equivalent oxide thicknesses (EOT's) < 0.7 nm, but higher k dielectrics and thinner interfacial layers are needed below 0.7 nm. copyright The Electrochemical Society.

Original languageEnglish (US)
Title of host publicationECS Transactions
Pages389-415
Number of pages27
Volume3
Edition3
DOIs
StatePublished - 2006
EventPhysics and Technology of High-k Gate Dielectrics 4 - 210th Electrochemical Society Meeting - Cancun, Mexico
Duration: Oct 29 2006Nov 3 2006

Other

OtherPhysics and Technology of High-k Gate Dielectrics 4 - 210th Electrochemical Society Meeting
CountryMexico
CityCancun
Period10/29/0611/3/06

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