Managing shared last-level cache in a heterogeneous multicore processor

Vineeth Mekkat, Anup Holey, Pen Chung Yew, Antonia Zhai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

65 Scopus citations

Abstract

Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as GPU cores onto the same die raise several new issues for sharing various on-chip resources. The shared last-level cache (LLC) is one of the most important shared resources due to its impact on performance. Accesses to the shared LLC in heterogeneous multicore processors can be dominated by the GPU due to the significantly higher number of threads supported. Under current cache management policies, the CPU applications' share of the LLC can be significantly reduced in the presence of competing GPU applications. For cache sensitive CPU applications, a reduced share of the LLC could lead to significant performance degradation. On the contrary, GPU applications can often tolerate increased memory access latency in the presence of LLC misses when there is sufficient thread-level parallelism. In this work, we propose Heterogeneous LLC Management (HeLM), a novel shared LLC management policy that takes advantage of the GPU's tolerance for memory access latency. HeLM is able to throttle GPU LLC accesses and yield LLC space to cache sensitive CPU applications. GPU LLC access throttling is achieved by allowing GPU threads that can tolerate longer memory access latencies to bypass the LLC. The latency tolerance of a GPU application is determined by the availability of thread-level parallelism, which can be measured at runtime as the average number of threads that are available for issuing. Our heterogeneous LLC management scheme outperforms LRU policy by 12.5% and TAP-RRIP by 5.6% for a processor with 4 CPU and 4 GPU cores.

Original languageEnglish (US)
Title of host publicationPACT 2013 - Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques
Pages225-234
Number of pages10
DOIs
StatePublished - Nov 18 2013
Event22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013 - Edinburgh, United Kingdom
Duration: Sep 7 2013Sep 11 2013

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013
Country/TerritoryUnited Kingdom
CityEdinburgh
Period9/7/139/11/13

Keywords

  • cache management policy
  • heterogeneous multicores
  • shared last-level cache

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