Abstract
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1 V and threshold voltage as low as 0.2 V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by upto 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when arbitrary number of threshold voltages are allowed.
Original language | English (US) |
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Pages | 139-144 |
Number of pages | 6 |
DOIs | |
State | Published - 1999 |
Event | Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) - San Diego, CA, USA Duration: Aug 16 1999 → Aug 17 1999 |
Conference
Conference | Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) |
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City | San Diego, CA, USA |
Period | 8/16/99 → 8/17/99 |