Low power SRAM design using hierarchical divided bit-line approach

Keyphrases

• Bitline 100%
• Low Power SRAM 100%
• SRAM Design 100%
• Line Capacitance 27%
• Hierarchical Level 18%
• Active Power 18%
• Access Time 18%
• Transistor 9%
• Power Consumption 9%
• Number of Levels 9%
• Number of Blocks 9%
• Voltage Swing 9%
• 6T SRAM Cell 9%
• Active Power Consumption 9%

Engineering

• Bit Line 100%
• Active Power 37%
• Bit-Line Capacitance 37%
• Electric Power Utilization 25%
• Access Time 25%
• Experimental Result 12%