A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stabilized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1995|
|Event||Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA|
Duration: Apr 30 1995 → May 3 1995