Low-power multiplier design using delayed evaluation

Gerald E. Sobelman, Donovan L. Raatz

Research output: Contribution to journalConference articlepeer-review

24 Scopus citations


A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stabilized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier.

Original languageEnglish (US)
Pages (from-to)1564-1567
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995


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