Abstract
Low power gate resizing can decrease the power dissipated in a technology mapped circuit while maintaining its critical path. Gate resizing operates as a post-mapping technique for power reduction by replacing some gates, which are faster than necessary, with smaller and slower gates from the underlying gate library. In this paper we propose a new transformation technique for combinational circuits referred to as buffer-redistribution. Buffer-redistribution is then used to model and solve the low-power discrete gate resizing problem in an exact manner in polynomial time and in a noniterative fashion for a complete gate library. Suboptimal solutions are obtained with incomplete gate libraries. In contrast past polynomial time techniques for gate resizing were either based on heuristics or based on much slower iterative exact algorithms. Simulation results on ISCAS85 benchmark circuits demonstrate 2.1%-54.1% power reduction based on the proposed buffer-redistribution based low-power gate resizing. Power savings from 0%-44.13% are demonstrated over the same circuits mapped for minimum area. The time required for resizing varies from 2.77s-1256.76s.
Original language | English (US) |
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Title of host publication | Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999 |
Editors | Stephen P. DeWeerth, D. Scott Wills |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 170-184 |
Number of pages | 15 |
ISBN (Electronic) | 0769500560, 9780769500560 |
DOIs | |
State | Published - 1999 |
Event | 1999 Conference on Advanced Research in VLSI, ARVLSI 1999 - Atlanta, United States Duration: Mar 21 1999 → Mar 24 1999 |
Publication series
Name | Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999 |
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Other
Other | 1999 Conference on Advanced Research in VLSI, ARVLSI 1999 |
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Country/Territory | United States |
City | Atlanta |
Period | 3/21/99 → 3/24/99 |
Bibliographical note
Publisher Copyright:© 1999 IEEE.