Low-power FIR digital filters using residue arithmetic

William L. Freking, Keshab K Parhi

Research output: Contribution to journalArticle

33 Citations (Scopus)

Abstract

This paper demonstrates that residue arithmetic can result in implementation of low-power FIR digital filters. It is shown that, for word-lengths up to 32 bits, the power consumption of residue-arithmetic-based FIR filters is dramatically less than two's-complement-based FIR filters. The power reduction is possible since the use of residue arithmetic transforms the filtering problem into multiple smaller word-length filters for various moduli which are operated in parallel. These compact filters can be operated with lower supply voltage for a specified sample speed, thus obtaining decreased power consumption compared to binary. Power reduction factors for residue arithmetic implementation become increasingly favorable as the system word-length is increased.

Original languageEnglish (US)
Pages (from-to)739-743
Number of pages5
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Volume1
StatePublished - Jan 1 1998

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FIR filters
Digital filters
Electric power utilization
Electric potential

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Low-power FIR digital filters using residue arithmetic. / Freking, William L.; Parhi, Keshab K.

In: Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, 01.01.1998, p. 739-743.

Research output: Contribution to journalArticle

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