This paper demonstrates that residue arithmetic can result in implementation of low-power FIR digital filters. It is shown that, for word-lengths up to 32 bits, the power consumption of residue-arithmetic-based FIR filters is dramatically less than two's-complement-based FIR filters. The power reduction is possible since the use of residue arithmetic transforms the filtering problem into multiple smaller word-length filters for various moduli which are operated in parallel. These compact filters can be operated with lower supply voltage for a specified sample speed, thus obtaining decreased power consumption compared to binary. Power reduction factors for residue arithmetic implementation become increasingly favorable as the system word-length is increased.
|Original language||English (US)|
|Number of pages||5|
|Journal||Conference Record of the Asilomar Conference on Signals, Systems and Computers|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1997 31st Asilomar Conference on Signals, Systems & Computers. Part 1 (of 2) - Pacific Grove, CA, USA|
Duration: Nov 2 1997 → Nov 5 1997