Low-power FIR digital filter architectures

Darren N. Pearson, Keshab K Parhi

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations


This paper presents a novel approach for low power implementations of finite impulse response (FIR) filters with less hardware overhead than traditional FIR implementations. Parallel or block processing with duplication of hardware can reduce power consumption; parallel processing by block size L requires the critical path to be charged in L times longer time as compared with the sequential implementation and the identical critical path can be charged in longer time with lower supply voltage which leads to lower power consumption. The hardware cost of this approach increases linearly with the block size L. In this paper we propose a general technique for block implementation of FIR filters which requires fewer multipliers than the straightforward block implementation. The use of this approach can lead to a further reduction in power consumption and hardware cost.

Original languageEnglish (US)
Pages (from-to)231-234
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995


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